The present disclosure relates to a method of manufacturing an integrated circuit (IC) device, and more particularly, to a method of manufacturing an IC device using a plurality of patterns.
With the development of electronic technology, semiconductor devices have been recently rapidly down-scaled. In the manufacturing of a highly integrated semiconductor device, a pattern formation process may become more difficult due to the micronization of a pattern size. For example, a line-and-space pattern with a repeated arrangement of a plurality of patterns may be more prone to warpage or collapse when a width of patterns is reduced and a space depth between patterns is increased.